Voice over Internet Protocol has created the need for telecommunications equipment to support the conversion from traditional telecom interfaces to packet interfaces. Traditional legacy telecom equipment was based upon a circuit switching fabric with time division multiplex switching (TDM), and TDM transport networks. In VoIP networks, VoIP Gateway equipment is located at the interface with conventional telephone equipment.
VoIP Gateway equipment includes some conventional components, such as line circuits (SLICS and CODECs). Digital Signal Processors (DSPs) and Network Processors (NP) are generally introduced to accomplish the conversion and interface from conventional circuit-switched equipment to the packet network.
Legacy telecom equipment was built with Plain Old Telephone System (POTS) line circuits, and/or T1/E1 circuits, and other higher bandwidth physical layer interfaces, all of which used TDM type serial bus interfaces as the standard interface of choice. This architecture was simple, scaleable, and commonly accepted throughout the industry.
Gateway designs with VoIP capability have not matured to the point where common bus interfaces exist, particularly between the DSP modules and Network Processor devices. Examination of commercial Network Processor devices reveals that many different I/O ports are supported including Utopia II, high-speed serial ports, Ethernet, and various parallel processor ports. Commercial NP devices have Ethernet as a common interface, particularly “Fast Ethernet” or Gigabit Ethernet (MII or GMII). MII is the Media Independent Interface, a standardized bus used to interconnect Ethernet MAC devices with Ethernet PHY devices.
The need to provide Ethernet for 10/100/1000 LAN traffic provides a persuasive argument that the NP port of choice should be Ethernet (MII or GMII), for all physical device ports including voice ports. The task of aggregating traffic from FXS/FXO (Port line circuit to subscriber telephone/Pots line circuit to central office) voice ports, T1/E1 ports and 10/100/1000 data ports (and possibly many other media ports), is one that is best done in an all Ethernet environment if possible.
The devices that interface all media with Ethernet are aggregated by a Network Processor. This is a relatively new philosophy for FXS/FXO ports, because it is proposed that most digital signal processing required for an FXS/FXO port be distributed onto the line interface circuit itself. While many integrated VoIP devices currently exist with DSP and RISC processors on-chip today, the intention to performing all DSP media processing as well as all packet processing, is not attractive due to voice port scaling issues. It is preferable to leave the NP functionality on a commercial HOST/NP in order to exploit the full potential of constantly improving processor technology and software development environments. The software environment appears to be increasingly based upon LINUX, Open Source software, and legacy application code.
The basic components of a typical VoIP gateway, IP-PBX, or Communication Server are shown in FIG. 1. The line circuits (SLIC/CODEC) 101 . . . 106 are typically the same devices used by traditional TDM equipment, and interface to DSP devices 121 . . . 123 (via TDM bus) to provide the necessary digital media processing to prepare the telephone signals for a VoIP network interface. Table 1 indicates some of the typical media processing tasks provided by DSP devices 121 . . . 123.
TABLE 1Media Processing FunctionsEcho cancellationNoise reductionVoice Codecs: G.711, G.729AB, G.723.1, G.726DTMF Tx/RxVAD/CNG/PLCT.38 and VBD Fax Relay3-way callingLost packet concealmentProgrammable Tone GenerationFSK (Caller ID)Adaptive Jitter BufferGain Control
The DSP devices 121 . . . 123 in turn interface to a Network Processor or Host processor 14 to perform the necessary packet processing to prepare the voice packets for transmission over a packet based network. The network processor 16 is associated with memory 16. The particular interface is not standardized, and many methods are can be used to implement the interface. This includes proprietary FPGA interfaces, or proprietary high-speed serial buses, Utopiall, etc. In the present example, an FPGA interface 18 is used.
Table 2 indicates some of the packet processing functions typically provided by a Network Processor. The functions provide by the SLICS 101 . . . 106 are shown in Table 3.
TABLE 2Network Processor FunctionsSignalling e.g. SIP, H.323, MGCPRTP/RTCPSecurity ProcessingFirewallCall-ProcessingPacket Re-ordering and other packet processing functionsSystem applications
TABLE 3SLIC functionsTransformer-less 2 W/4 W conversion2 W Impedance matchingAdaptive Linear Trans-hybrid ECANBalanced Sinusoidal Ringing GenerationPWM controller for external switching power supply (per line).Off-hook and dial pulse detectionTip & Ring ground over-current protection24 mA constant current feed *Line Polarity ReversalMeter Pulse InjectionRing trip detectionProgrammable DC feedGround Button DetectBattery voltage feedingTransversal current sensingLongitudinal current sensingOverload protectionOn-hook transmissionRinging amplification
In small systems the DSP and NP are often integrated into a single device to provide the most cost-effective integrated solution. This present invention does not apply to such a case if the application does not require expandability of voice ports.
There is however a need for a simple-to-use, scaleable VoIP line circuit that can be easily interfaced to a central Host processor.